1 ? fn9083.3 isl6520b single synchronous buck pulse-width modulation (pwm) controller the isl6520b makes simple work out of implementing a complete control scheme for a dc/dc stepdown converter. designed to drive n-channel mosfets in a synchronous buck topology, the isl6520b int egrates the control, output adjustment and monitoring functions into a single 8 lead package. the isl6520b provides simple, single feedback loop, voltage-mode control with fast transient response. the output voltage can be precisely regulated to as low as 0.8v, with a maximum tolerance of 1.5% over-temperature and line voltage variations. a fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. the error amplifier featur es a 15mhz gain-bandwidth product and 8v/ s slew rate which enables high converter bandwidth for fast transient performance. the resulting pwm duty cycles range from 0% to 100%. features ? operates from +5v input ? 0.8v to v in output range - 0.8v internal reference - 1.5% over line voltage and temperature ? drives n-channel mosfets ? simple single-loop control design - voltage-mode pwm control ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty cycle ? small converter size - 300khz fixed frequency oscillator - internal soft start - 8 ld soic or 16ld 4mmx4mm qfn ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free plus anneal available (rohs compliant) applications ? power supplies for microprocessors -pcs - embedded controllers ? subsystem power supplies - pci/agp/gtl+ buses - acpi power control - sstl-2 and ddr sdram bus termination supply ? cable modems, set-top boxes, and dsl modems ? dsp and core communications processor supplies ? memory supplies ? personal computer peripherals ? industrial power supplies ? 5v-input dc/dc regulators ? low-voltage distributed power supplies ordering information part number part marking temp. range (c) package pkg. dwg. # isl6520bcb* 6520 bcb 0 to +70 8 ld soic m8.15 ISL6520BCBZ* (note) 6520 bcbz 0 to +70 8 ld soic (pb-free) m8.15 isl6520bcr* 65 20bcr 0 to +70 16 ld 4x4 qfn l16.4x4 isl6520bcrz* (note) 65 20bcrz 0 to +70 16 ld 4x4 qfn (pb-free) l16.4x4 isl6520bir* 65 20bir -40 to +85 16 ld 4x4 qfn l16.4x4 isl6520birz* (note) 65 20birz -40 to +85 16 ld 4x4 qfn (pb-free) l16.4x4 isl6520eval1 evaluation board *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which ar e rohs compliant and compatible with both snpb and pb-free sol dering operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet july 23, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2005, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9083.3 july 23, 2007 pinouts block diagram typical application 5 6 8 7 4 3 2 1 ugate gnd phase fb vcc comp/sd boot lgate nc comp/sd nc fb boot ugate gnd nc nc nc phase nc lgate nc vcc nc isl6520b (8 ld soic) top view isl6520b (16 ld qfn) top view 1 3 4 15 16 14 13 2 12 10 9 11 6 578 + - + - oscillator inhibit pwm comparator error amp v cc pwm gnd fb comp/sd 0.8v gate control logic boot ugate phase 20 a fixed 300khz + - lgate vcc softstart por and 5v v out fb comp/sd ugate phase boot vcc gnd lgate 5 7 63 2 1 8 4 isl6520b r s r offset c i c f r f l out d boot c boot c bulk c dcpl c hf c out v in q u q l r pullup shutdown isl6520b
3 fn9083.3 july 23, 2007 absolute maximum rati ngs thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . +15.0v upper driver supply voltage, v boot - v phase . . . . . . . . 7.0v (dc) 8.0v (<10ns pulse width, 10 j) input, output or i/o voltage . . . . . . . . . . . gnd -0.3v to vcc +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 10% ambient temperature range - isl6520bc . . . . . . . . . 0c to +70c junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 95 n/a qfn package (notes 2, 3). . . . . . . . . . 45 7 maximum junction temperature (plastic package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. parameter symbol test conditions min typ max units vcc supply current nominal supply i vcc 2.6 3.2 3.8 ma power-on reset rising vcc por threshold por 4.19 4.30 4.50 v vcc por threshold hysteresis -0.25- v oscillator frequency f osc isl6520bc, vcc = 5v 250 300 340 khz isl6520bi, vcc = 5v 230 300 340 khz ramp amplitude v osc -1.5-v p-p reference reference voltage tolerance isl6520bc -1.5 - +1.5 % isl6520bi -2.5 +2.5 % nominal reference voltage v ref -0.800- v error amplifier dc gain (note 4) - 88 - db gain-bandwidth product gbwp (note 4) - 15 - mhz slew rate sr (note 4) - 8 - v/ s gate drivers upper gate source current i ugate-src v boot - v phase = 5v, v ugate = 4v - -1 - a upper gate sink current i ugate-snk -1- a lower gate source current i lgate-src v vcc = 5v, v lgate = 4v - -1 - a lower gate sink current i lgate-snk -2- a disable disable threshold v disable -0.8- v note: 4. limits should be considered ty pical and are not production tested isl6520b
4 fn9083.3 july 23, 2007 functional pin description vcc this pin provides the bias supply for the isl6520b, as well as the lower mosfet?s gate. connect a well-decoupled 5v supply to this pin. fb this pin is the inverting input of the internal error amplifier. use this pin, in combinati on with the comp/sd pin, to compensate the voltage-control feedback loop of the converter. gnd this pin represents the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. phase connect this pin to the upper mosfet?s source. ugate connect this pin to the upper mosfet?s gate. this pin provides the pwm-controlled gate drive for the upper mosfet. this pin is also monitored by the adaptive shoot- through protection circuitry to determine when the upper mosfet has turned off. boot this pin provides ground refe renced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive a logic-level n-channel mosfet. comp/sd this pin is the output of the erro r amplifier. use this pin, in combination with the fb pin, to compensate the voltage- control feedback loop of the converter. pulling comp/sd to a level below 0.8v disables the controller. disabling the isl6520b causes the oscillator to stop, the lgate and ugate outputs to be held low, and the softstart circuitry to re-arm. the comp/sd pin must be pulled above 0.8v to terminate shutdown. this may be done through a pullup resistor tied between vcc and comp/sd. the recommended range of resistor values to use as the pullup resistor is between 50k and 100k . lgate connect this pin to the lower mosfet?s gate. this pin provides the pwm-controlled gate drive for the lower mosfet. this pin is also monitored by the adaptive shoot- through protection circuitry to determine when the lower mosfet has turned off. functional description initialization the isl6520b automatically initializes u pon receipt of power. the power-on reset (por) function continually monitors the bias voltage at the vcc pin. the por function initiates the soft start operation. soft start the isl6520b is held in reset with both ugate and lgate driven to ground until the por threshold on vcc has been reached and the comp/sd pin has been pulled above 0.8v. if comp is not actively pulled high following por the internal 20 a current sink will hold comp/sd low and the device will remain in reset. comp/sd can eith er be statically tied to vcc through a pullup resistor or driven high through a resistor to terminate reset. the recommended range of resistor values to use as the pullup resistor is between 50k and 100k . following reset the isl6520b provides a 1024 clock cycle settling period (~3.4ms) prior to initiating softstart. at the conclusion of the settling period the comp/sd pin is driven to 0.8v for 24 clock cycles (~75 s) to discharge the compensation network. soft start of the regulated output is generated by imposing an internal offset on the fb pin which ramps down from 0.8v to 0v over the next 2048 clock cycles (~6.8ms). total time from end of reset to completion of soft-start is 10.2ms. pulling comp/sd below 0.8v or vcc dropping below minimum por initiates another reset. current sinking the isl6520b incorporates a mosfet shoot-through protection method which allows a converter to sink current as well as source current. care should be exercised when designing a converter with the isl6520b when it is known that the converter may sink current. when the converter is sinking cu rrent, it is behaving as a boost converter that is regulati ng it?s input voltage. this means that the converter is boosting current into the v cc figure 1. soft start interval time (2ms/div.) v out 500mv/div. v comp/sd 1v/div. isl6520b
5 fn9083.3 july 23, 2007 rail, which supplies the bias vo ltage to the isl6520b. if there is nowhere for this current to go, such as to other distributed loads on the v cc rail, through a voltage limiting protection device, or other methods, the capacitance on the v cc bus will absorb the current. this situation will allow voltage level of the v cc rail to increase. if the vo ltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the isl6520b, then the ic will experience an irreversible failure and the converter will no longer be operational. ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close toget her as possible, using ground plane construction or single point grounding. figure 2 shows the critical powe r components of the converter. to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. the components shown in figure 2 should be located as close together as possible. please note that the capacitors c in and c o may each represent numerous physical capacitors. locate the isl6520b within 3 inches of the mosfets, q 1 and q 2 . the circuit traces for the mosfets? gate and source connections from the isl6520b must be sized to handle up to 1a peak current. figure 3 shows the circuit tr aces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the comp/sd pin and locate the resistor, r oscet close to the comp/sd pin because the internal current source is only 20 a. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. all components used for feedback compensation should be located as close to the ic a practical. feedback compensation figure 4 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (err or amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). l o c o lgate ugate phase q 1 q 2 v in v out return isl6520b c in load figure 2. printed circuit board power and ground planes or islands figure 3. printed circuit board small signal layout guidelines +5v isl6520b gnd vcc boot d 1 l o c o v out load q 1 q 2 phase +v in c boot c vcc figure 4. voltage-mode buck converter compensation design v out reference l o c o esr v in v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 2 c 1 comp/sd v out fb z fb isl6520b z in comparator driver detailed compensation components phase v e/a + - + - z in osc isl6520b
6 fn9083.3 july 23, 2007 the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage v osc . modulator break frequency equations the compensation network consists of the error amplifier (internal to the isl6520b) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. the equations below relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 4. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place 1 st zero below filter?s double pole (~75% f lc ). 3. place 2 nd zero at filter?s double pole. 4. place 1 st pole at the esr zero. 5. place 2 nd pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin - repeat if necessary. compensation break frequency equations figure 5 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 5. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the graph of figure 5 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45 degrees. include worst case component variations when determining phase margin. component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. t he filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by t he esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-es r capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr avai lable in larger case sizes. however, the equivalent seri es inductance (e sl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a sing le large case capacitor. f lc 1 2 x l o x c o ------------------------------------------ - = f esr 1 2 x esr x c o ------------------------------------------- - = (eq. 1) f z1 1 2 x r 2 x c 1 ------------------------------------ = f z2 1 2 x r 1 r 3 + () x c 3 ------------------------------------------------------ - = f p1 1 2 x r 2 x c 1 x c 2 c 1 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = f p2 1 2 x r 3 x c 3 ------------------------------------ = (eq. 2) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 20log f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / v osc ) modulator gain (r 2 /r 1 ) figure 5. asymptotic bode plot of converter gain closed loop gain isl6520b
7 fn9083.3 july 23, 2007 output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time re quired to change the inductor current. given a sufficiently fast control loop design, the isl6520b w ill provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor cu rrent from an initial current value to the transient current le vel. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors phys ically close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but ca ution must be exercised with regard to the capacitor surge currentrating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. mosfet selection/considerations the isl6520b requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor. the switching losses seen when sourcing curr ent will be different from the switching losses seen when sinking current. when sourcing current, the upper mosfet realizes most of the switching losses. the lower switch real izes most of the switching losses when the converter is sinking current (see the equations below). these equations assume linear voltage- current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower mosfet?s body diode. the gate-charge lo sses are dissipated by the isl6520b and don't heat the mosfets. however, large gate- charge increases the switching interval, t sw which increases the mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. given the reduced available gate bias voltage (5v), logic-level or sub-logic-level transistors should be used for both n-mosfets. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot- i = v in - v out fs x l v out v in v out = i x esr x (eq. 3) t rise = l x i tran v in - v out t fall = l x i tran v out (eq. 4) p lower = io 2 x r ds(on) x (1 - d) where: d is the duty cycle = v out / v in , t sw is the combined switch on and off time, and f s is the switching frequency. losses while sourcing current losses while sinking current p lower io 2 r ds on () 1d ? () 1 2 -- - io ? v in t sw f s + = p upper io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = p upper = io 2 x r ds(on) x d (eq. 5) isl6520b
8 fn9083.3 july 23, 2007 through protection present aboard the isl6520b may be circumvented by these mosfets if they have large parasitic impedences and/or capacitances that would inhibit the gate of the mosfet from being discharged below it?s threshold level before the complement ary mosfet is turned on. figure 6 shows the upper gate drive (boot pin) supplied by a bootstrap circuit from v cc . the boot capacitor, c boot , develops a floating supply voltage referenced to the phase pin. the supply is refreshed to a voltage of v cc less the boot diode drop (v d ) each time the lower mosfet, q 2 , turns on. isl6520b dc/dc converter application circuit figure 7 shows an application circuit of a dc/dc converter. detailed information on the circuit, including a complete bill- of-materials and circuit board description, can be found in application note an9932. +5v isl6520b gnd lgate ugate phase boot vcc +5v note: note: v g-s v cc c boot d boot q1 q2 + - figure 6. upper gate drive bootstrap v g-s v cc -v d + v d - component selection notes: c in - each 330mf 6.3wvdc, sanyo 6tpb330m or equivalent. c out - each 330mf 6.3wvdc, sanyo 6tpb330m or equivalent. d1 - 30ma schottky diode, ma732 or equivalent l 1 - 3.1 h inductor, panasonic p/n etq-p6f2rolfa or equivalent. q 1 , q 2 - fairchild mosfet; huf76143. figure 7. 5v to 3.3v 15a dc/dc converter +5v v out fb comp/sd ugate phase boot vcc gnd lgate + 5 7 6 3 2 1 8 4 isl6520b + 3.16k l 1 c out d 1 0.1 f c in 2 x 1 f q 1 q 2 u 1 0.1 f por ref osc + - - + 3 x 330 f 2 x 330 f 0.1 f 1.00k 10.0k 470pf 8200pf 60.4 18000pf and soft start 50k isl6520b
9 fn9083.3 july 23, 2007 isl6520b small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9083.3 july 23, 2007 isl6520b quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
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